[Lf] [Fwd: LF: RE DDS Sources in receivers]

[Andre' Kesteloot]

Talbot Andrew wrote:

> Yes, but a 100 Hz step on a single loop 136MHz PLL will mean that you
> will need a very long loop time constant - of the order of a second or
> more.   Phase noise on the VCO outside this bandwidth will then remain
> uncorrected, and will appear divided down in bandwidth by 1000.  You
> will also be unlikely to filter out the 100 Hz sidebands.  When the
> signal is divided down, then the classic FM situation will appear where
> the FM sidebands ar still at the same spacing but at different levels -
> ie. you will still have 100 / 200 / 300 Hz sidebands but at lower
> levels.   A double loop synth would help but the complexity involved
> here sureley means looking at other techniques.
> I suspect that the residual spurii will be worse than the 60 - 70dBc for
> a DDS design and spaced much wider.
>
> As a test last night, I mixed the output of my DDS LF generator set to
> generate 59.8kHz, (DDS clocked at 5MHz) with an off air MSF signal at
> 60kHz.   The resulting 200 Hz output was low pass filtered and fed to
> the soundcard and monitored with Gram and also on similar software for
> the 56002EVm - EVMSPEC..  The only sidebands visible were those caused
> by the switching of the MSF carrier, no sign of the jitter mentioned by
> Klaus, DJ5HG.  But, as Spectran only gives about 70dB dynamic range
> anyway. EVMSPEC  can just about cope with 80dB dynamic range, and again
> there was again nothing obvious
> The next test is to take two DDS sources,  mix them together and try to
> generate this 'noise' that is supposed to be present.  I have certainly
> never seen anything in the past that is worse than the 60dBc or whatever
> specified.
>
> About 10 years ago I witnessed some tests being done on an early
> (Plessey I think) GaAs logic based DDS clocked at UHF.  The D/A in that
> was low resolution, probably an 8 bit flash design, and sprogs were
> many.  But they were as predicted, 30 - 40dB levels typically and at
> frequencies that could be calculated in advance.  The wanted output was
> a clean carrier.   This design was soon superceeded by the more modern
> ones around now.   I note that my IC746 has three DDS's in it, but
> interestingly each one has a separate discrete R-2R ladder chain for its
> D/A, the switches being inside the (FPGA ?) special function chips
> making up the logic board.
>
> I still maintain that a DDS is one of the cleanest in terms of phase
> noise, and certainly the most flexible frequency source around these
> days.  The cleanest frequency source achievable, ever, will likely
> always be a straight well designed crystal oscillator in a Butler
> configuration.
>
> What are the implications of 60dBc sideband / phase noise anyway ?  They
> are only going to matter if an INBAND signal is 60dB up on the wanted
> one, and isn't that quite likely to give problems elsewhere in the
> processing chain ?
>
> Andy  G4JNT
>
> > I was thinking of an alternative route, by using a classic PLL in the
> > VHF
> > range and devide it down to LF. A PLL system working on 136MHz in
> > 100Hz
> > steps can be devided by 1000, giving you 0.1Hz steps on 136kHz.
> > Dividing by
> > 1000 will also result in a significant phasenoise reduction.
> >
>
> --
> The Information contained in this E-Mail and any subsequent correspondence
> is private and is intended solely for the intended recipient(s).
> For those other than the recipient any disclosure, copying, distribution,
> or any action taken or omitted to be taken in reliance on such information is
> prohibited and may be unlawful.