[Lf] DDS Sources in receivers]

[Andre' Kesteloot]

Klaus von der Heide wrote:

> Andy, G4JNT wrote:
>
> > A DDS does indeed generate spurious products, but these are precisely
> > characterisable and at a level defined by the chip manufacturer.  Apart
> > from image and harmonics, they are a function of the DDS process and NOT
> > SUBJECT to poor layout construction etc whereas a phase locked loop
> > synthesizer is unbelievably sensitive to noise etc in the control
> > circuitry caused by poor design.   Furthermore, the spurs are usually
> > well away from the wanted frequency so properly applied filtering will
> > eliminate any possible spurious responses.
>
> In my previous mail I pointed out, that the spurs generated by a DDS
> are due to an imprecise implementation of the sine function. This
> imprecision is a result of a compromise between the diverging goals,
> speed and precision.
> The spurs can be made as low as you want. They are a consequence of
> the DDS-IMPLEMENTATION, not of the DDS-PRINCIPLE.  If you base
> the design on a loadable sine table of variable length, you will
> be able to work entirely without spurs in almost all cases.
>
> Example: You want to generate 19.200 kHz on a DSP at a sample rate
> of 48.000 kHz. Generate a sine table of the 5 values
> sin(2*pi*k/5) with k = 0,1,2,3,4  and wrap around in this table
> at a step of 2. Interpolation is not neccessary, so no spurs.
>
> Hardware implementations mostly use ROM-sine-tables of fixed size.
> Then sine values at phases between adjacent table points have to be
> computed. Example:
> The same situation as above; use a sine table of 256 values.
> Let the first phase be 0, then the second is  p = (0 + step)mod 256
> where   step = 256*19.2/48.0 = 102.4
> To calculate  sine(2*pi*p/256)  the nearest table point p0 to p
> is chosen, i.e. in the above example:  p = 102.4;  p0 = 102;
> p1 = 0.4  with  p = p0 + p1
> Let   s = table(p0)              (the sine value from the table)
> and   c = table((p0+64)mod 256)  (the correspondent cosine value)
> and  dp = p1*2*pi/256 .
> Then compute   x = s + dp*(c - dp*(s/2 + dp*c/6))  (Taylor-series)
> Using this simple algorithm the value x never differs from the exact
> sin(2*pi*p/256) by more than  5e-9.  Spurs are less than -165 dB.
>
> Implementation of this algorithm on a DSP costs about 30 instruction
> cycles in contrast to only one if simply the nearest lower table
> point is taken. The gain achieved by this factor 30 in computational
> effort is about 130 dB in spur suppression.
>
> It is this hardware (or software) simplification that causes the
> spurs, not the DDS in principle.  Surely future DDS-chips will
> use advanced algorithms to minimize spurs.
>
> > Any one who advocates using a PLL just to 'clean up' a DDS is
> asking for
> > the worst of all worlds.
>
> The phase noise of a PLL is proportional to the frequency division
> factor used in the PLL. A clean-up-PLL will not use any divider.
> So the phase noise could be kept low.  But, off course, it will be
> present at the win of very low spurs.  Nevertheless, I prefer a more
> precise DDS-implementation instead of such a clean-up which would
> reduce the usable frequency range.
>
> Two years ago I made my own board with four synchronous AD9850
> driven individually via the printer port. That is very valuable
> for many purposes. In fact, I also use this board in receiver
> applications, especially where frequency stability is the main
> point.
>
> 73 de Klaus, DJ5HG